Designing Digital Circuits in Multi-Valued Logic

— In the last few decades we have witnessed an increase in CPU performance, which has been made possible thanks to the increase in the clock frequency and the increase in the number of transistors in the unit of space. In the last few years, however, we reached the limit for the clock and for the miniaturization of the transistor grid. Beyond this growth new problems arose such as the disposal of the produced heat and the minimum distance to be respected between elements for the electrical signals transfer. So the chip makers, to further increase the processing power of the processors, started to insert more cores on the same chip. The presence of several cores undoubtedly improves performance and improves consumption, but the ability to transfer data between cores and components remains limited by the number of pins of the cores themselves. Furthermore, it is necessary to manage the synchronization between cores during the access to common resources and all those multi-core architectures typical problems. This article provides a different approach to improve the computing capacity of the CPUs that is based on the extension of the binary system in a multi-value coding system or, commonly, called MVL. Although this direction has already been explored, the idea behind the study is in the representation of the generic function in the MVL domain. This representation has a link to the binary system and a surprisingly greater simplicity of the corresponding digital circuits (combinatorial and sequential). A different mathematical approach is thus provided for the realization of the multivalue logic gates. This could enable the use of different data encoding systems no longer linked to the voltage value of a signal but to other physical quantities as it happens at present, for example, in the world of telecommunications.


I. INTRODUCTION
The chip makers have always looked to improve performance by trying to make increasingly powerful and faster CPUs by focusing on increasing the clock frequency and inserting a greater number of transistors in the unit of space. In recent decades, the number of CPU transistors followed the famous Moore law. Unfortunately, due to the level of miniaturization achieved, it was no longer possible to increase neighter the density of the transistors, nor the clock frequency (another factor that influences the computing power), because new problems arose, in addition to the ability to operate at inertial distances, linked to the signal transfer speed between components and also to the heat produced by the components overheating (see [1]).
As the increase in the density of transistors on the surface had reached the limit, some have hypothesized to increase the number through the thickening of the die. However, having a greater thickness of the die can lead to a significant increase in costs, for this reason some studies have shown that the number of transistors can be increased by using a double layer of the die to form a crystal grid in whose nodes [transistors are located. This approach, duplicates the number of transistors and makes the die thicker [2].
However, the strategy adopted by the chipmakers has been to improve the computing power by constructing CPUs with multiple cores within the same chip, enabling processing parallelism. This approach undoubtedly improves performance but introduces new problems because that processing is distributed on the cores. These cores must be synchronized to access common resources or collaborate to a common goal. Moreover, the management of interrupts is more complex than a single-core. Finally, the limit of the transfer capacity of the cores cannot be exceeded, because it depends on the number of connections and the clock frequency. Power management also becomes a crucial factor when building high-performance architectures, as the articles [3], [4] and [5] demonstrates.
In this article we will discuss a different approach based on the possibility of building a high performance computer architecture by making digital components that work intrinsically in multivalue logic (MVL). The need to build efficient machines that worked in MVL, with low consumption was considered in [6].
A ternary computer hypothesis has been historically treated in [7] where the author observed that if the circuit complexity depended roughly on the product of the base size used (R) multiplied by the number of digits of the maximum representable number (N), the economically best basis was e=2,718. The article pointed out that if it were possible to build components that when increasing the representation base (R) size complexity and cost don't grow, the best choice would be to adopt the largest possible base.
The idea of designing circuits that work in MVL has recently been treated from the canonical point of view, using post-order algebras of degree greater than or equal to two, also in [8]. Some studies showed that the methods used in the Boolean algebra, such as the Quine Mc-Cluskey method shown in [9], are applicable. However, the idea that inspired this work is the scalability of the solution with respect to the chosen base, the simple realization of the circuits and the maintenance of a close relationship with the binary system. The ability to build any circuit in MVL will allow to build processors, memories and I/O devices able to operate, with the same number of connections, at a greater throughput compared to the binary case. The ternary logic was the first studied extension of the binary algebra ( [10] and [11]), but also inspired the realization of processors working on the base 3 [12]. Also the quaternary logic, being power of two, inspired many research works ( [13] and [14]). In the literature we also find valuable contributions on MVL as [15] and [16], also from the point of view of the verification of hardware circuits [17].
However, with the present work we will demonstrate how it is possible to define a reduced set of mathematical operators that are able to perform any function in the chosen domain independently from the base, similar to what happens for universal operators (NAND and NOR) in the case of Boolean algebra. The proposed idea is based on the use of one-digit arithmetic operations (multiplication and sum) together with the functions reported in the binary domain (the selectors). Multivalue operators will be described in Session II from the external point of view, as if they were black boxes, without considering the internal functionality or the modes of transferring the signals.
Research and technological innovation will provide, in the near future, the best answers for the realization of these components. Session III is organized in two parts: the first concerns the process of creating an example of combinational circuit (half-adder); the second one is the construction of a memory element for MVL information. Section IV gives the conclusion and oulines the future research.

II. MATERIAL AND METHOD
Without losing generality we can consider the algebra in base 3 and then we can extend the operators to any domain with n-values. Although we have extended the discrete domain by a single value, for example a word of only 10 digits passes from 1024 combinations in the binary number system to about 59k in the ternary one.
So we can imagine a function like a black box that receives input values I 0 , I 1 ,..., I p-2 , I p-1 and returns an output U that represents the value assumed by the function at the inputs (combinatorial circuit). With p inputs we have x=3 p combinations of the inputs that originate 3 x different functions. In a generic algebra with n values we will have x=n p e n x different functions.
1) Unary functions: in the context of the n n possible unary functions (27 in the ternary case) we consider n functions, which reduce the n-ario domain into the binary one. In particular we will call them selection functions, or selectors, and we will indicate them with the letter S.
In an algebra with n values there are n selectors each one for any symbol of the domain. If c ∈ T the selection function S c (I) answers the value 1 when in input (I) the value c is present and zero in the other cases.
In the ternary case the functions S 0 , S 1 and S 2 are: We want to create a normal form that, similarly to the case of the min-term or max-term of Boolean algebra, considers groups of selectors of the input variables, modulated by the constant corresponding to the row, joined by an aggregation fuction .
The properties required for the two operators op 1 e op 2 are: X op 1 0 = 0 (2) X op 1 1 = X (3) X op 2 0 = X (4) Although there are various functions that satisfy the properties (2) and (3), restricting the field of interest to the four arithmetic operations above, a possible candidate for op 1 that satisfies the properties (2) and (3) is the multiplication operation.
Summarizing, in the ternary number system we can represent any two-input function (F) using its description of the truth table. The method is similar to the binary case: we have to consider all possible combination of the input variables and for each of them consider the corrisponding value of the function. we can write that F is calculated as the union of the nine exclusive and not overlaped cases: F = k 0 S 0 (I 1 )S 0 (I 0 )+ k 1 S 0 (I 1 )S 1 (I 0 ) + ... + k 8 S 2 (I 1 )S 2 (I 0 ) that is: where: • k i is the value assumed in the row corresponding to the number i, with k i ∈{0,1,2}; • c j (i) is the j-th digit of the number i, represented in base n = 3, with j∈{0,1}:  The proof of the validity of the formula is simple: only one group of selectors can obtain the value 1 at a time, as only one configuration of the inputs is possible, being discrete. The other groups will get value 0.
The group of selectors corresponding to the input configuration will be multiplied by the related value k i (property (1)) which, added to the others with null value groups (property (2)), will be returned as output (property (3)).

B. N-ary algebra
The interesting thing is that we can go further by generalizing the representation base (n) and describing with the same method any function (F) with a predefined number of operands (p) within the set of n x possibile functions, with x=n p . Also in this case we can write the table of values:   TABLE VII  TRUTH TABLE OF In a similar way to what has already been seen in the case n = 3, it is possible to represent F according to the inputs I 0 , I 1 , ...,I p-1 : (8) where:

A. The realization process of a combinational circuit in MVL
In this section we will show the algorithm to design the multivalue circuit corresponding to a generic function in the multi-value domain. The proposed algorithm is based on four sequential steps: 1) building the truth table that describes exhaustively the function to be implemented through all the possible combinations of the inputs (n p , logic with n values and function with p operands), 2) for each non-zero element of the column that describes the function in the truth table, multiply the value for the row selector group, 3) the function is given by the sum of the groups of terms identified in point 2).
To simplifity the use of the algorithm, and in analogy with [8] in order to grasp the differences between different representation systems, we will implement the two-digit half-hadder circuit (I 1 and I 2 ) in base 4.

B. Basic element for an MVL memory
In this section, we present our design of a D flip-flop which is based on an extension of binary D flip-flop. In a D flip-flop the next state Q(t+1) is characterized by a function of both the current state Q(t) and the D data input. The next state Q(t+1) could be defined by: (12) or (13) these two equations can be transformed in a fuzzy domain by replacing the binary operators by fuzzy operators as shown in [20] [6]. Using min-max type operation and fuzzy negation we can write the following transformation: (14) (15) The symbol represents min operation and represents max operation. Because these equations do not transform D flip-flop to the fuzzy domain, the authors proposed a different equation. The proposed circuit, however, is not simple to realize, therefore starting from the assumption that normally to construct memory elements, a clock is used that allows to restrict the sampling interval of the input D. In this case the transfer function can be written through the operators we have defined in Session II: It can be understood easily that working with the flip-flop shown in Fig. 3, the value of the input D is posted to the output Q(t) when the CLK values is 1, otherwise (CLK=0) the circuit store the previous value: Q(t+1)=Q(t).
The corresponding digital circuit will then be: Excitation table for this circuit is shown in Table IX.  The proposed solution is not opposed to multi-core architectures, since it describes how the internal operating logic of a future CPU could be and therefore nothing prevents the creation of multi-core architectures with MVL.